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integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 pin configuration recommended application: ati rs780 systems using amd k8 processors output features: integrated series resistors on all differential outputs. 1 - greyhound compatible k8 cpu pairs 5 - low-power differential src pairs 2 - low-power differential chipset southbridge src pairs 1 - selectable low-power differential 100mhz non-spread sata/ src output 1 - selectable low-power differential src / 27mhz single ended outputs 1 - selectable ht3 100mhz low-power differential hypertransport clock / ht66mhz single ended outputs 1 - 48mhz usb clock 3 - 14.318mhz reference clock 2 - low-power differential atig pairs 5- dedicated clkreq# pins programmable system clock chip for ati rs780 - k8 tm based systems *other names and brands may be claimed as the property of others. key specifications: cpu outputs cycle-to-cycle jitter < 150ps src outputs cycle-to-cycle jitter < 125ps sb_src outputs cycle-to-cycle jitter < 125ps +/- 100ppm frequency accuracy on cpu, src, atig 0ppm frequency accuracy on 48mhz features/benefits: power saving features: optional separate supply rail for src low voltage i/o - ~33% power saving when 1.5v is used for this rail spread spectrum for emi reduction outputs may be disabled via smbus external crystal load capacitors for maximum frequency accuracy 48mhz_0 vdd48 x2 x1 gndref ref0/sel_htt66 ref1/sel_sata ref2/sel_27 vddref vddhtt htt0t_lprs/66m htt0c_lprs/66m gndhtt pd# cpukg0t_lprs cpukg0c_lprs 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd48 1 48 vddcpu smbclk 2 47 vddcpu_io smbdat 3 46 gndcpu vdd 4 45 clkreq1#* src7c_lprs/27mhz_ns 5 44 clkreq2#* src7t_lprs/27mhz_ss 6 43 gndsata gnd 7 42 src6t/satat_lprs src4c_lprs 8 41 src6c/satac_lprs src4t_lprs 9 40 vddsata gndsrc 10 39 clkreq3#* vddsrc_io 11 38 clkreq4#* src3c_lprs 12 37 sb_src0t_lprs src3t_lprs 13 36 sb_src0c_lprs src2c_lprs 14 35 vddsb_src src2t_lprs 15 34 vddsb_src_io vddsrc 16 33 gndsb_src 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vddsrc_io gndsrc src1c_lprs src1t_lprs src0c_lprs src0t_lprs *clkreq0# gndatig vddatig_io vddatig atig1c_lprs atig1t_lprs atig0c_lprs atig0t_lprs sb_src1c_lprs sb_src1t_lprs ICS9LPRS480
2 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 mlf pin description pin # pin name pin type description 1 gnd48 gnd ground pin for the 48mhz outputs 2 smbclk in clock pin of smbus circuitry, 5v tolerant. 3 smbdat i/o data pin for smbus circuitry, 5v tolerant. 4 vdd27 pwr 3.3v power supply for src/27mhz output and 27mhz ss pll 5 src7c_lprs/27mhz_ns out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed)/27mhz 3.3v single-ended non-spread output for discrete graphics 6 src7t_lprs/27mhz_ss out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed)/27mhz 3.3v single-ended spreading output for discrete graphics 7 gnd27 gnd ground for the src/27mhz outputs 8 src4c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 9 src4t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 10 gndsrc gnd ground pin for the src outputs 11 vddsrc_io pwr power supply for differential src outputs, nominal 1.05v to 3.3v 12 src3c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 13 src3t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 14 src2c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 15 src2t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 16 vddsrc pwr supply for src core, 3.3v nominal 17 vddsrc_io pwr power supply for differential src outputs, nominal 1.05v to 3.3v 18 gndsrc gnd ground pin for the src outputs 19 src1c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 20 src1t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 21 src0c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 22 src0t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 23 *clkreq0# in clock request pin for src0 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 24 gndatig gnd ground pin for the atig outputs 25 vddatig_io pwr power supply for differential atig outputs, nominal 1.05v to 3.3v 26 vddatig pwr power supply for atig core, nominal 3.3v 27 atig1c_lprs out complementary clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 28 atig1t_lprs out true clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 29 atig0c_lprs out complementary clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 30 atig0t_lprs out true clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 31 sb_src1c_lprs out complement clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 32 sb_src1t_lprs out true clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed
3 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 mlf pin description (continued) pin # pin name pin type description 33 gndsb_src gnd ground pin for the sb_src outputs 34 vddsb_src_io pwr power supply for differential sb_src outputs, nominal 1.05v to 3.3v 35 vddsb_src pwr supply for sb src pll core, 3.3v nominal 36 sb_src0c_lprs out complement clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 37 sb_src0t_lprs out true clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 38 clkreq4#* in clock request pin for src4 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 39 clkreq3#* in clock request pin for src3 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 40 vddsata pwr power supply for sata core logic, nominal 3.3v 41 src6c/satac_lprs out complement clock of low power differential src/sata clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 42 src6t/satat_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 43 gndsata gnd ground pin for the src outputs 44 clkreq2#* in clock request pin for src2 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 45 clkreq1#* in clock request pin for src1 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 46 gndcpu gnd ground pin for the cpu outputs 47 vddcpu_io pwr power supply for differential cpu outputs, nominal 1.05v to 3.3v 48 vddcpu pwr supply for cpu core, 3.3v nominal 49 cpukg0c_lprs out complementary signal of low-power differential push-pull amd k8 "greyhound" clock with integrated series resistor. (no 33 ohm series resistor needed) 50 cpukg0t_lprs out true signal of low-power differential push-pull amd k8 "greyhound" clock with integrated series resistor.(no 33 ohm series resistor needed) 51 pd# in enter /exit power down. 0 = power down, 1 = normal operation. 52 gndhtt pwr ground pin for the htt outputs 53 htt0c_lprs/66m out complementary signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) / 1.8v single ended 66mhz hyper transport clock 54 htt0t_lprs/66m out true signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) /1.8v single ended 66mhz hyper transport clock 55 vddhtt pwr supply for htt clocks, nominal 3.3v. 56 vddref pwr ref, xtal power supply, nominal 3.3v 57 ref2/sel_27 i/o 14.318 mhz reference clock, 3.3v/3.3v latched input to select 27mhz ss and non ss on src7 0 = 100mhz differential spreading src clock, 1 = 27mhz non-spreading singled clock on pin 5 and 27mhz spread clock on pin 6. 58 ref1/sel_sata i/o 14.318 mhz 3.3v reference clock./ 3.3v tolerant latched input to select function of src6/sata output 0 = 100mhz differential spreading src clock, 1 = 100mhz non-spreading differential sata clock 59 ref0/sel_htt66 i/o 14.318 mhz 3.3v reference clock./ 3.3v tolerant latched input to select hyper transport clock frequency. 0 = 100mhz differential htt clock, 1 = 66mhz 3.3v single ended htt clock 60 gndref gnd ground pin for the ref outputs. 61 x1 in crystal input, nominally 14.318mhz 62 x2 out crystal output, nominally 14.318mhz 63 vdd48 pwr power pin for the 48mhz outputs and core. 3.3v 64 48mhz_0 out 48mhz clock output.
4 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 pin configuration ref1/sel_sata 1 64 ref2/sel_27 ref0/sel_htt66 2 63 vddref gndref 3 62 vddhtt x1 4 61 htt0t_lprs/66m x2 5 60 htt0c_lprs/66m vdd48 6 59 gndhtt 48mhz_0 7 58 pd# gnd48 8 57 cpukg0t_lprs smbclk 9 56 cpukg0c_lprs smbdat 10 55 vddcpu vdd27 11 54 vddcpu_io src7c_lprs/27mhz_ns 12 53 gndcpu src7t_lprs/27mhz_ss 13 52 clkreq1#* gnd27 14 51 clkreq2#* src4c_lprs 15 50 gndsata src4t_lprs 16 49 src6t/satat_lprs gndsrc 17 48 src6c/satac_lprs vddsrc_io 18 47 vddsata src3c_lprs 19 46 clkreq3#* src3t_lprs 20 45 clkreq4#* src2c_lprs 21 44 sb_src0t_lprs src2t_lprs 22 43 sb_src0c_lprs vddsrc 23 42 vddsb_src vddsrc_io 24 41 vddsb_src_io gndsrc 25 40 gndsb_src src1c_lprs 26 39 sb_src1t_lprs src1t_lprs 27 38 sb_src1c_lprs src0c_lprs 28 37 atig0t_lprs src0t_lprs 29 36 atig0c_lprs *clkreq0#30 35atig1t_lprs gndatig 31 34 atig1c_lprs vddatig_io 32 33 vddatig 64-pin tssop * internal pull-up resistor ** internal pull-down resistor ICS9LPRS480
5 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 tssop pin description pin # pin name pin type description 1 ref1/sel_sata i/o 14.318 mhz 3.3v reference clock./ 3.3v tolerant latched input to select function of src6/sata output 0 = 100mhz differential spreading src clock, 1 = 100mhz non-spreading differential sata clock 2 ref0/sel_htt66 i/o 14.318 mhz 3.3v reference clock./ 3.3v tolerant latched input to select hyper transport clock frequency. 0 = 100mhz differential htt clock, 1 = 66mhz 3.3v single ended htt clock 3 gndref gnd ground pin for the ref outputs. 4 x1 in crystal input, nominally 14.318mhz 5 x2 out crystal output, nominally 14.318mhz 6 vdd48 pwr power pin for the 48mhz outputs and core. 3.3v 7 48mhz_0 out 48mhz clock output. 8 gnd48 gnd ground pin for the 48mhz outputs 9 smbclk in clock pin of smbus circuitry, 5v tolerant. 10 smbdat i/o data pin for smbus circuitry, 5v tolerant. 11 vdd27 pwr 3.3v power supply for src/27mhz output and 27mhz ss pll 12 src7c_lprs/27mhz_ns out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed)/27mhz 3.3v single-ended non-spread output for discrete graphics 13 src7t_lprs/27mhz_ss out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed)/27mhz 3.3v single-ended spreading output for discrete graphics 14 gnd27 gnd ground for the src/27mhz outputs 15 src4c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 16 src4t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 17 gndsrc gnd ground pin for the src outputs 18 vddsrc_io pwr power supply for differential src outputs, nominal 1.05v to 3.3v 19 src3c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 20 src3t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 21 src2c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 22 src2t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 23 vddsrc pwr supply for src core, 3.3v nominal 24 vddsrc_io pwr power supply for differential src outputs, nominal 1.05v to 3.3v 25 gndsrc gnd ground pin for the src outputs 26 src1c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 27 src1t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 28 src0c_lprs out complement clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 29 src0t_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 30 *clkreq0# in clock request pin for src0 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 31 gndatig gnd ground pin for the atig outputs 32 vddatig_io pwr power supply for differential atig outputs, nominal 1.05v to 3.3v
6 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 tssop pin description (continued) pin # pin name pin type description 33 vddatig pwr power supply for atig core, nominal 3.3v 34 atig1c_lprs out complementary clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 35 atig1t_lprs out true clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 36 atig0c_lprs out complementary clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 37 atig0t_lprs out true clock of low-power differential push-pull pci-express pair with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 38 sb_src1c_lprs out complement clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 39 sb_src1t_lprs out true clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 40 gndsb_src gnd ground pin for the sb_src outputs 41 vddsb_src_io pwr power supply for differential sb_src outputs, nominal 1.05v to 3.3v 42 vddsb_src pwr supply for sb src pll core, 3.3v nominal 43 sb_src0c_lprs out complement clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 44 sb_src0t_lprs out true clock of low power differential chipset-to-chipset src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed 45 clkreq4#* in clock request pin for src4 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 46 clkreq3#* in clock request pin for src3 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 47 vddsata pwr power supply for sata core logic, nominal 3.3v 48 src6c/satac_lprs out complement clock of low power differential src/sata clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 49 src6t/satat_lprs out true clock of low power differential src clock pair. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) 50 gndsata gnd ground pin for the src outputs 51 clkreq2#* in clock request pin for src2 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 52 clkreq1#* in clock request pin for src1 outputs. if output is selected for control, then that output is controlled as follows: 0 = enabled, 1 = low-low 53 gndcpu gnd ground pin for the cpu outputs 54 vddcpu_io pwr power supply for differential cpu outputs, nominal 1.05v to 3.3v 55 vddcpu pwr supply for cpu core, 3.3v nominal 56 cpukg0c_lprs out complementary signal of low-power differential push-pull amd k8 "greyhound" clock with integrated series resistor. (no 33 ohm series resistor needed) 57 cpukg0t_lprs out true signal of low-power differential push-pull amd k8 "greyhound" clock with integrated series resistor.(no 33 ohm series resistor needed) 58 pd# in enter /exit power down. 0 = power down, 1 = normal operation. 59 gndhtt pwr ground pin for the htt outputs 60 htt0c_lprs/66m out complementary signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) / 1.8v single ended 66mhz hyper transport clock 61 htt0t_lprs/66m out true signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 50ohm shunt resistor to gnd and no 33 ohm series resistor needed) /1.8v single ended 66mhz hyper transport clock 62 vddhtt pwr supply for htt clocks, nominal 3.3v. 63 vddref pwr ref, xtal power supply, nominal 3.3v 64 ref2/sel_27 i/o 14.318 mhz reference clock, 3.3v/3.3v latched input to select 27mhz ss and non ss on src7 0 = 100mhz differential spreading src clock, 1 = 27mhz non-spreading singled clock on pin 12 and 27mhz spread clock on pin 13.
7 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 general description block diagram the ICS9LPRS480 is a main clock synthesizer chip that provides all clocks required for ati rs7xx-based systems.using amd processors. an smbus interface allows full control of the device. power groups vdd vddio gnd 63 1 usb_48 outputs 47 src/27mhz outputs 16 10,18 src logic core 11,17 src differential outputs (io's) 35 33 sb_src core logic 34 sb_src differential outputs (io's) 40 43 src/sata differential output 26 24 atig core logic 25 atig differential outputs (io's) 48 43 cpukg core logic 47 cpukg differential outputs (io's) 55 52 httclk output 56 60 ref outputs description pin number ref(2:0) cpukg osc 14.318 mhz sb_src(1:0) src(5:0) 100mhz 48mhz_(1:0) x1 x2 fixed pll ss sb_src 200mhz pd# sel_sata smbclk smbdat control logic htt0/66mhz 100mhz src6/sata 100mhz dif/66mhz ss pll cpu/htt, src, atig clkreq(5:0)# 100mhz atig(2:0) sel_htt66 sel_27 27mhz ss pll 27mhz ss pll src7c/27mhz_ns src7t/27mhz_ss
8 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 table1: cpu/htt, src and atig frequency selection table byte 0 bit0 bit3 bit2 bit1 bit0 ss_en cpu fs3 cpu fs2 cpu fs1 cpu fs0 sel_htt66 = 1 sel_htt66 = 0 0 0000173.63 57.88 86.81 86.81 -13% 0 0001177.17 59.06 88.58 88.58 -11% 0 0010180.78 60.26 90.39 90.39 -10% 0 0011184.47 61.49 92.24 92.24 -8% 0 0100188.24 62.75 94.12 94.12 -6% 0 0101192.08 64.03 96.04 96.04 -4% 0 0110196.00 65.33 98.00 98.00 -2% 0 0111200.00 66.67 100.00 100.00 0% 0 1000204.00 68.00 102.00 102.00 2% 0 1001208.08 69.36 104.04 104.04 4% 0 1010212.24 70.75 106.12 106.12 6% 0 1011216.49 72.16 108.24 108.24 8% 0 1100220.82 73.61 110.41 110.41 10% 0 1101225.23 75.08 112.62 112.62 13% 0 1110229.74 76.58 114.87 114.87 15% 0 1111234.33 78.11 117.17 117.17 17% 1 0000173.63 57.88 86.81 86.81 -13% 1 0001177.17 59.06 88.58 88.58 -11% 1 0010180.78 60.26 90.39 90.39 -10% 1 0011184.47 61.49 92.24 92.24 -8% 1 0100188.24 62.75 94.12 94.12 -6% 1 0101192.08 64.03 96.04 96.04 -4% 1 0110196.00 65.33 98.00 98.00 -2% 1 0111 200.00 66.67 100.00 100.00 0% 1 1000204.00 68.00 102.00 102.00 2% 1 1001208.08 69.36 104.04 104.04 4% 1 1010212.24 70.75 106.12 106.12 6% 1 1011216.49 72.16 108.24 108.24 8% 1 1100220.82 73.61 110.41 110.41 10% 1 1101225.23 75.08 112.62 112.62 13% 1 1110229.74 76.58 114.87 114.87 15% 1 1111234.33 78.11 117.17 117.17 17% -0.5% spread % cpu overclock % off byte 3 htt single-ended cpu (mhz) differential htt src/atig
9 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 table 2: sb_src frequency selection table byte 0 bit0 bit3 bit2 bit1 bit0 ss_en sb fs3 sb fs2 sb fs1 sb fs0 0 000080.00 -20% 0 000181.25 -19% 0 001082.63 -17% 0 001184.00 -16% 0 010085.25 -15% 0 010186.63 -13% 0 011088.00 -12% 0 011189.25 -11% 0 100090.63 -9% 0 100192.00 -8% 0 101093.25 -7% 0 101194.63 -5% 0 110096.00 -4% 0 110197.25 -3% 0 111098.63 -1% 0 1111100.00 0% 1 000080.00 20% 1 000181.25 -19% 1 001082.63 -17% 1 001184.00 -16% 1 010085.25 -15% 1 010186.63 -13% 1 011088.00 -12% 1 011189.25 -11% 1 100090.63 -9% 1 100192.00 -8% 1 101093.25 -7% 1 101194.63 -5% 1 110096.00 -4% 1 110197.25 -3% 1 111098.63 -1% 1 1111100.00 0% src (mhz) spread % byte 4 -0.50% sb_src overclock % off
10 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 table3: 27mhz_spread and frequency selection table ss3 ss2 ss1 ss0 byte 4 bit 7 byte 4 bit 6 byte 4 bit 5 byte 4 bit 4 00000 27.00 00001 27.00 00010 27.00 00011 27.00 00100 27.00 00101 27.00 00110 27.00 00111 27.00 01000 27.00 01001 27.00 01010 27.00 01011 27.00 01100 27.00 01101 27.00 01110 27.00 01111 27.00 10000 27.00-0.50down 10001 27.00-1.00down 10010 27.00-1.50down 10011 27.00-2.00down 10100 27.00-0.75down 10101 27.00-1.25down 10110 27.00-1.75down 10111 27.00-2.25down 1 1 0 0 0 27.00 +/-0.25 cente r 1 1 0 0 1 27.00 +/-0.5 center 1 1 0 1 0 27.00 +/-0.75 center 1 1 0 1 1 27.00 +/-1.0 center 1 1 1 0 0 27.00 +/-0.25 cente r 1 1 1 0 1 27.00 +/-0.5 cente r 1 1 1 1 0 27.00 +/-0.75 center 1 1 1 1 1 27.00 +/-1.0 center ss enable b2b1 27mhz_spread (mhz) no spread spread % (when enabled)
11 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 true output complement output true output complement output 1 0 enable running running running running 0 x x low/20k low low/20k low 1 1 enable running running low/20k low xx disable low/20k low low/20k low note: 20k means 20kohm pull down 1 enable running running running running 0 enable low low low hi-z differential output power management table singled-ended power management table free-run clkreq# selected pd# clkreq# smbus register oe 48mhz pd# smbus register oe ref(2:0) 27mhz htt66mhz
12 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 absolute maximum rating parameter symbol conditions min typ max units notes 3.3v suppl y volta g evddxxx -3.3 gnd + 3.9v v 1 storage temperature ts - -65 150 c 1 ambient operating temp tambient - 070c 1 case temperature tcase - 115 c 1 input esd protection hbm esd prot - 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. electrical characteristics - input/supply/common output parameters parameter symbol conditions* min typ max units notes 3.3v core supply voltage vddxxx - 3.135 3.3 3.465 v 1 input high voltage v ih vdd = 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage v il vdd = 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high voltage - sel_27 v ih vdd = 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage - sel_27 v il vdd = 3.3 v +/-5% v ss - 0.3 0.4 v 1 input high voltage - sel_sata v ih vdd = 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage - sel_sata v il vdd = 3.3 v +/-5% v ss - 0.3 0.4 v 1 input high voltage - sel_htt66 v ih vdd = 3.3 v +/-5% 2 v dd + 0.3 v 1 input low voltage - sel_htt66 v il vdd = 3.3 v +/-5% v ss - 0.3 0.4 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull- up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 low threshold input- high voltage v ih_fs vdd = 3.3 v +/-5% 0.7 v dd + 0.3 v 1 low threshold input- low voltage v il_fs vdd = 3.3 v +/-5% v ss - 0.3 0.35 v 1 operating current i dd3. 3op 3.3v vdd current, all outputs driven 225 ma 1 powerdown current i dd3. 3p d all diff pairs low/low 2 ma 1 input frequency f i vdd = 3.3 v +/-5% 14.31818 mhz 2 pin inductance l p in 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization t stab from vdd power-up or de- assertion of pd to 1st clock 1.8 ms 1 modulation frequency triangular modulation 30 33 khz 1 tdrive_pd cpu output enable after pd de-assertion 300 us 1 tfall_pd pd fall time of 5 ns 1 trise_pd pd rise time of 5 ns 1 smbus voltage v ddsmb 2.7 5.5 v 1 low-level output voltage v olsmb @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullupsmb 46 ma1 smbclk/smbdat clock/data rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 smbclk/smbdat clock/data fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. input low current input capacitance 2 input frequency should be measured at the ref pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs.
13 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 ac electrical characteristics - low-power dif outputs: cpukg and htt parameter symbol conditions min typ max units notes crossing point variation ? v cross single-ended measurement 140 mv 1,2,5 frequency - cpu f cpu spread specturm on 198.8 200 mhz 1,3 frequency - htt f htt spread specturm on 99.4 100 mhz 1,3 lon g term accurac y pp ms p read s p ecturm off -300 +300 pp m1,11 rising edge slew rate s rise differential measurement 0.5 10 v/ns 1,4 falling edge slew rate s fall differential measurement 0.5 10 v/ns 1,4 slew rate variation t slvar sin g le-ended measurement 20 % 1 cpu, dif htt jitter - cycle to cycle cpuj c2c differential measurement 150 ps 1,6 accumulated jitter t jacc see notes 1 ns 1,7 peak to peak differential voltage v d(pk-pk) differential measurement 400 2400 mv 1,8 differential voltage v d differential measurement 200 1200 mv 1,9 duty cycle d cyc differential measurement 45 55 % 1 amplitude variation ? v d change in v d dc cycle to cycle -75 75 mv 1,10 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 notes on electrical characteristics: 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 3 minimum fre q uenc y is a result of 0.5% down s p read s p ectrum 6 max difference of t cycle between an y two ad j acent c y cles. 7 accumulated tjc.over a 10 s time period, measured with jit2 tie at 50ps interval. 8 vd(pk-pk) is the overall magnitude of the differential signal. 11 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of cl k rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#. it is measured using a +/-75mv window centered on the average cross point where clk meets clk#. 4 differential measurement through the range of 100 mv, differential signal must remain monotonic and within slew rate spec when crossin g throu g h this re g ion. 9 vd(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0v vd. vd(max) is the largest amplitude allowed. 2 single-ended measurement at crossing point. value is maximum ? minimum over all time. dc value of common mode is not important 10 the difference in magnitude of two adjacent vd_dc measurements. vd_dc is the stable post overshoot and ring-back part of the ac electrical characteristics - low-power dif outputs: src, sb_src and atig parameter symbol conditions min typ max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar sin g le-ended measurement 20 % 1 maximum output voltage v hi gh includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 src, atig, jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 src[5:0] skew src skew differential measurement 250 ps 1 sb_src[1:0] skew src skew differential measurement 100 ps 1 atig[2:0] skew src skew differential measurement 100 ps 1 notes on electrical characteristics: 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the volta g e where clk = clk# 4 onl y a pp lies to the differential risin g ed g e ( clk risin g and clk# fallin g) 6 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk
14 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 66.67mhz output nominal 14.9955 15.0045 ns 2 66.67mhz output spread 14.9955 15.0799 ns 2 output high voltage v oh i oh = -1 ma 1.6 1.8 v 1 output low voltage v ol i ol = 1 ma 0 0.2 v 1 rise time t r1 v ol = 0.36 v, v oh = 1.44 v 1.5 ns 1 fall time t f1 v oh = 1.44 v, v ol = 0.36 v 1.5 ns 1 duty cycle d t1 v t = 0.9 v 45 55 % 1 jitter, cycle to cycle t j c y c-c y c v t = 0.9 v 300 ps 1 jitter, long term t ltj v t = 0.9 v 1 ns 1 *ta = 0 - 70c; suppl y volta g e vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref is at 14.31818mhz electrical characteristics - single-ended htt 66mhz clock htt66 clock period t period electrical characteristics - usb - 48mhz parameter symbol conditions* min typ max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t p eriod 48.00mhz output nominal 20.8229 20.8344 ns 2 clock low time t low measure from < 0.6v 9.3750 11.4580 ns 2 clock high time t hi g h measure from > 2.0v 9.3750 11.4580 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rise time t r_usb v ol = 0.4 v, v oh = 2.4 v 0.5 1.5 ns 1 fall time t f_usb v oh = 2.4 v, v ol = 0.4 v 0.5 1.5 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 group skew t skew v t = 1.5 v 250 ps 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 130 ps 1,2 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. 2 ics recommended and/or chipset vendor layout guidelines must be followed to meet this specification output low current i ol output high current i oh
15 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 electrical characteristics - ref-14.318mhz parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t p eriod 14.318mhz output nominal 69.8270 69.8550 ns 2 clock low time t low measure from < 0.6v 30.9290 37.9130 ns 2 clock high time t hi g h measure from > 2.0v 30.9290 37.9130 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.5 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.5 ns 1 skew t sk1 v t = 1.5 v 250 ps 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 300 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5%, cl = 5 pf with rs = 33 ? (unless otherwise specified) 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz electrical characteristics - 27mhz parameter symbol conditions min typ max units notes -50 50 1,2 -15 15 1,2,3 clock period t p eriod 27.000mhz output nominal 37.0365 37.0376 ns 2 output high voltage(27ss, 27nss) v oh i oh = -1 ma 2.1 v 1,10 output low voltage v ol i ol = 1 ma 0.55 v 1 v oh = 1.0 v -29 ma 1,10 v oh = 3.135 v -23 ma 1,10 v ol = 1.95 v 29 ma 1,10 v ol = 0.4 v 27 ma 1,10 edge rate t slewr/f rising/falling edge rate v t @ 20%-80% 12 4v/ns1 duty cycle d t1 v t = 1.5 v 45 55 % 1 t lt j long term (10us) 300 ps 1 t jcyc-cyc v t = 1.5 v 200 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 10 v d d = 3.3v jitter output high current i oh output low current i ol long accuracy ppm see tperiod min-max values ppm
16 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 general smbus serial interface information for the ICS9LPRS480 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the beginning byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controller (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
17 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: latched input readback output enable control register byte 0 name description type 0 1 default bit 7 sel_htt66 readback hypertransport select r 100mhz differential htt clock 66 mhz 3.3v single- ended htt clock latch bit 6 sel_sata readback sata select r src6/sata pair is src ss capable output src6/sata pair is sata non-spread output latch bit 5 ref0_oe output enable rw hi-z enabled 1 bit 4 ref1_oe output enable rw hi-z enabled 1 bit 3 ref2_oe output enable rw hi-z enabled 1 bit 2 0 bit 1 48mhz_0_oe output enable rw low enabled 1 bit 0 ss_enable spread spectrum enable (cpu, src, sb_src, atig) rw spread off spread on 0 smbus table:output enable control register byte 1 name control function type 0 1 default bit 7 src7/27mhz_oe output enable rw low/low enabled 1 bit 6 src6/sata_oe enable output enable rw low/low enabled 1 bit 5 0 bit 4 src4_oe output enable rw low/low enabled 1 bit 3 src3_oe output enable rw low/low enabled 1 bit 2 src2_oe output enable rw low/low enabled 1 bit 1 src1_oe output enable rw low/low enabled 1 bit 0 src0_oe output enable rw low/low enabled 1 smbus table: output enable and 48mhz slew rate control register byte 2 name control function type 0 1 default bit 7 sb_src1_oe output enable rw low/low enabled 1 bit 6 sb_src0_oe output enable rw low/low enabled 1 bit 5 1 bit 4 1 bit 3 atig1_oe output enable rw low/low enabled 1 bit 2 atig0_oe output enable rw low/low enabled 1 bit 1 27mhz_ss_enable spread spectrum enable 27mhz_ss rw spread off spread on 0 bit 0 reserved reserved rw - - x smbus table: cpu/htt frequency control register byte 3 name control function type 0 1 default bit 7 cpu0_oe output enable rw low/low enable 1 bit 6 sel_27 readback src7/27mhz select r src7 output 27mhz output latch bit 5 1 bit 4 htt/66mhz_oe output enable rw low/low enabled 1 bit 3 cpu_fs3 cpu frequency select rw 0 bit 2 cpu_fs2 cpu frequency select rw 1 bit 1 cpu_fs1 cpu frequency select rw 1 bit 0 cpu_fs0 cpu frequency select lsb rw 1 48mhz_0_slew rate rw see cpu/htt/src/atig frequency select table default value corresponds to 200mhz. note that the htt frequency tracks the cpu frequency. these bits program the slew rate of the single ended outputs. the maximum slew rate is 1.9v/ns and the minimum slew rate is 1.1v/ns. the slew rate selection is as follows: 11 = 1.9v/ns 10 = 1.6v/ns 01 = 1.1v/ns 00 = tristated slew rate control reserved reserved reserved
18 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: sb_src frequency control register byte 4 name control function type 0 1 default bit 7 s3 rw 0 bit 6 s2 rw 0 bit 5 s1 rw 0 bit 4 s0 rw 0 bit 3 sb_src_fs3 sb_src frequency select rw 1 bit 2 sb_src_fs2 sb_src frequency select rw 1 bit 1 sb_src_fs1 sb_src frequency select rw 1 bit 0 sb_src_fs0 sb_src freq. select lsb rw 1 smbus table: 27mhz slew rate control register byte 5 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 1 bit 4 1 bit 3 sb_src source sb_src source selection rw sb_src pll src pll 1 bit 2 0 bit 1 0 bit 0 0 smbus table: i/o vout control register byte 6 name control function type 0 1 default bit 7 src diff amp rw 00 = 700mv 01 = 800mv 0 bit 6 src diff amp rw 10 = 900mv 11 = 1000mv 1 bit 5 cpu diff amp rw 00 = 700mv 01 = 800mv 0 bit 4 cpu diff amp rw 10 = 900mv 11 = 1000mv 1 bit 3 sb_src diff amp rw 00 = 700mv 01 = 800mv 0 bit 2 sb_src diff amp rw 10 = 900mv 11 = 1000mv 1 bit 1 x bit 0 x smbus table: vendor & revision id register byte 7 name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 see sb_src frequency select table. 27_ssc spread select s[1:0]: 00 = -0.5% default, 01 =1.0%, 10 = -1.5%, 11 = -2%. see table 3: 27mhz_spread, lcdclk spread and frequency selection table for additional selections. reserved src differential output amplitude control sb_src differential output amplitude control cpu differential output amplitude control reserved reserved revision id vendor id reserved reserved these bits program the slew rate of the single ended outputs. the maximum slew rate is 1.9v/ns and the minimum slew rate is 1.1v/ns. the slew rate selection is as follows: 11 = 1.9v/ns 10 = 1.6v/ns 01 = 1.1v/ns 00 = tristated 27m_ns_slew rate slew rate control rw 27m_ss_slew rate slew rate control rw
19 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: byte count register byte 8 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 bc5 byte count bit 5 (msb) rw 0 bit 4 bc4 byte count bit 4 rw 0 bit 3 bc3 byte count bit 3 rw 1 bit 2 bc2 byte count bit 2 rw 1 bit 1 bc1 byte count bit 1 rw 1 bit 0 bc0 byte count bit 0 (lsb) rw 1 smbus table: watchdog timer control register byte 9 name control function type 0 1 default bit 7 hwd_en watchdog hard alarm enable rw disable and reload hartd alarm timer, clear wd hard status bit. enable timer 0 bit 6 swd_en watchdog soft alarm enable rw disable enable 0 bit 5 wd hard status wd hard alarm status r normal alarm x bit 4 wd soft status wd soft alarm status r normal alarm x bit 3 wdtctrl watch dog alarm time base control rw 290ms base 1160ms base 0 bit 2 hwd2 wd hard alarm timer bit 2 rw 1 bit 1 hwd1 wd hard alarm timer bit 1 rw 1 bit 0 hwd0 wd hard alarm timer bit 0 rw 1 smbus table: wd timer safe frequency control register byte 10 name control function type 0 1 default bit 7 swd2 wd soft alarm timer bit 2 rw 1 bit 6 swd1 wd soft alarm timer bit 1 rw 1 bit 5 swd0 wd soft alarm timer bit 0 rw 1 bit 4 wd sf4 rw 0 bit 3 wd sf3 rw 0 bit 2 wd sf2 rw 1 bit 1 wd sf1 rw 1 bit 0 wd sf0 rw 1 smbus table: cpu pll frequency control register byte 11 name control function type 0 1 default bit 7 n div2 n divider prog bit 2 rw x bit 6 n div1 n divider prog bit 1 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x these bits represent the number of watch dog time base units that pass before the watch alarm expires. default is 7 x 290ms = 2s. watch dog safe freq programming bits the decimal representation of m and n divider in byte 11 and 12 will configure the vco frequency. default at power up = byte 3 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) . m divider programming bits these bits represent the number of watch dog time base units that pass before the watch alarm expires. default is 7 x 290ms = 2s. determines the number of bytes that are read back from the device. default is 0f hex. these bits configure the safe frequency that the device returns to if the watchdog timer expires. the value show here corresponds to the power up default of the device. see the various frequency select tables for the exact frequencies. reserved reserved
20 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: cpu pll frequency control register byte 12 name control function type 0 1 default bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x smbus table: cpu pll spread spectrum control register byte 13 name control function type 0 1 default bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: cpu pll spread spectrum control register byte 14 name control function type 0 1 default bit 7 x bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x smbus table: cpu output divider register byte 15 name control function type 0 1 default bit 7 cpu ndiv0 lsb n divider programming rw x bit 6 x bit 5 x bit 4 x bit 3 cpudiv3 rw 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 x bit 2 cpudiv2 rw 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 x bit 1 cpudiv1 rw 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 x bit 0 cpudiv0 rw 0011:/15 ; 0111:/18 1011:/36 ; 1111:/72 x smbus table: sb_src frequency control register byte 16 name control function type 0 1 default bit 7 n div2 n divider prog bit 2 rw x bit 6 n div1 n divider prog bit 1 rw x bit 5 m div5 rw x bit 4 m div4 rw x bit 3 m div3 rw x bit 2 m div2 rw x bit 1 m div1 rw x bit 0 m div0 rw x cpu m/n programming. reserved n divider programming b(10:3) the decimal representation of m and n divider in byte 11 and 12 will configure the vco frequency. default at power up = byte 3 rom table. vco frequency = 14.318 x ndiv(10:0)/mdiv(5:0) . reserved reserved reserved spread spectrum programming b(7:0) bytes 13 and 14 set the cpu/htt/src/atig spread pecentage.please contact ics for the appropriate values. m divider programming bit (5:0) the decimal representation of m and n divider in byte 16 and 17 configure the sb_src vco frequency. see m/n caculation tables for vco frequency formulas. spread spectrum programming b(14:8) bytes 13 and 14 set the cpu/htt/src/atig spread pecentage.please contact ics for the appropriate values. cpu divider ratio programming bits
21 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: sb_src frequency control register byte 17 name control function type 0 1 default bit 7 n div10 rw x bit 6 n div9 rw x bit 5 n div8 rw x bit 4 n div7 rw x bit 3 n div6 rw x bit 2 n div5 rw x bit 1 n div4 rw x bit 0 n div3 rw x smbus table: sb_src spread spectrum control register byte 18 name control function type 0 1 default bit 7 ssp7 rw x bit 6 ssp6 rw x bit 5 ssp5 rw x bit 4 ssp4 rw x bit 3 ssp3 rw x bit 2 ssp2 rw x bit 1 ssp1 rw x bit 0 ssp0 rw x smbus table: sb_src spread spectrum control register byte 19 name control function type 0 1 default bit 7 ssp15 rw x bit 6 ssp14 rw x bit 5 ssp13 rw x bit 4 ssp12 rw x bit 3 ssp11 rw x bit 2 ssp10 rw x bit 1 ssp9 rw x bit 0 ssp8 rw x smbus table: sb_src output divider control register byte 20 name control function type 0 1 default bit 7 sb_src ndiv0 lsb n divider programming rw x bit 6 x bit 5 x bit 4 x bit 3 sb_srcdiv3 rw 0000:/2 ; 0100:/4 1000:/8 ; 1100:/16 x bit 2 sb_srcdiv2 rw 0001:/3 ; 0101:/6 1001:/12 ; 1101:/24 x bit 1 sb_srcdiv1 rw 0010:/5 ; 0110:/10 1010:/20 ; 1110:/40 x bit 0 sb_srcdiv0 rw 0011:/15 ; 0111:/18 1011:/36 ; 1111:/72 x smbus table: device id register byte 21 name control function type 0 1 default bit 7 device id7 r 0 bit 6 device id6 r 1 bit 5 device id5 r 1 bit 4 device id4 r 1 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 1 bit 0 device id0 r 0 76 hex reserved src divider ratio programming bits spread spectrum programming bit(7:0) sb_src m/n programming. bytes 18 and 19 set the the sb_src spread pecentages. please contact ics for the appropriate values. device id reserved reserved spread spectrum programming bit(14:8) bytes 18 and 19 set the the sb_src spread pecentages. please contact ics for the appropriate values. n divider programming byte16 bit(7:0) and byte15 bit(7:6) the decimal representation of m and n divider in byte 16 and 17 configure the sb_src vco frequency. see m/n caculation tables for vco frequency formulas.
22 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 smbus table: clkreq# configuration register byte 22 name control function type 0 1 default bit 7 cpu/htt/src/atig m/n en cpu/htt/src/atig pll m/n prog. enable rw m/n prog. disabled m/n prog. enabled 0 bit 6 sb_src m/n en sb_src m/n prog. enable rw m/n prog. disabled m/n prog. enabled 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x smbus table: clkreq# configuration register byte 23 name control function type 0 1 default bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 clkreq4#_enable clkreq4# controls src4 rw not controlled controlled 0 bit 3 clkreq3#_enable clkreq3# controls src3 rw not controlled controlled 0 bit 2 clkreq2#_enable clkreq2# controls src2 rw not controlled controlled 0 bit 1 clkreq1#_enable clkreq1# controls src1 rw not controlled controlled 0 bit 0 clkreq0#_enable clkreq0# controls src0 rw not controlled controlled 0 smbus table: test mode configuration register byte 24 name control function type 0 1 default bit 7 test_md_sel selects test mode rw normal mode all ou p uts are ref/n 0 bit 6 diag enable# diag enable cpu and lcd pll rw reset forces b24[6:4,2,0] to 0 diag mode enabled 0 bit 5 cpu pll_lock signal cpu pll lock detect r unlocked locked hw bit 4 27mhz pll_lock signal 27mhz pll lock detect r unlocked locked hw bit 3 fixed pll_lock signal fixed pll lock detect r unlocked locked hw bit 2 src pll_lock signal fixed pll lock detect r unlocked locked hw bit 1 frequency check primary pll or external crystal frequency accuracy r not accurate accurate hw bit 0 pwrgd status power on reset status r invalid voltage levels on any of the vdds. ckpwrgd is not asserted or external xtal not detected. valid voltage levels exist on all the vdd. ckpwrgd is asserted and external xtal is detected. hw smbus table:slew rate select register byte 25 name control function type 0 1 default bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 1 bit 4 1 bit 3 1 bit 2 1 bit 1 1 bit 0 1 rw ref1_slew rate rw slew rate control rw ref0_slew rate slew rate control ref2_slew rate slew rate control these bits program the slew rate of the single ended outputs. the maximum slew rate is 1.9v/ns and the minimum slew rate is 1.1v/ns. the slew rate selection is as follows: 11 = 1.9v/ns 10 = 1.6v/ns 01 = 1.1v/ns 00 = tristated
23 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 ordering information 9lprs480 y klft example: designation for tape and reel packaging lead free, rohs compliant package type k = mlf revision designator device type xxxx y k lf t e top view or anvil singulation a3 l n (ref.) e e e e (ref. ) (ref. ) (ref. ) (typ.) if a1 even e2 d2 d2 2 a c 0.08 c e2 2 2 2 1 sawn singulation index area seating plane are even thermal base odd b (n - 1)x n 1 chamfer 4x 0.6 x 0.6 max optional d d & & n d n d n e n e & n d n e (n - 1)x e *due to package size constraints actual top side marking may differ from the full orderable part number. dimensions (mm) symbol min. max. a0.81.0 n 64 a1 0 0.05 n d 16 a3 n e 16 b 0.18 0.3 e d x e basic d2 min. / max. 7.00 7.25 e2 min. / max. 7.00 7.25 l min. / max. 0.30 0.50 0.25 reference 0.50 basic 9.00 x 9.00 thermally enhanced, very thin, fine pitch quad flat / no lead plastic package symbol 64l
24 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 ordering information 9lprs480 y glft example: designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator device type xxxx y g lf t minmaxminmax a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations minmaxminmax 64 16.90 17.10 .665 .673 10-0039 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0. 319 basic 0.50 basic 0. 020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 index area 12 n d e1 e seating plane a1 a a2 e - c - -- b c l aaa c
25 integrated circuit systems, inc. ICS9LPRS480 1391d?02/02/09 this product is protected by united states patent no. 7,342,420 and other patents. revision history rev. issue date description page # a 7/8/2008 going to release. - b 7/29/2008 removed table 4 and updated 27mhz electrical characteristics. 10-11 c 9/18/2008 updated input/supply/common output parameters. 12 d 2/2/2009 changed rs value from 22 ohm to 33 ohm. 14, 15

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